Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Microelectronics Reliability

Volumn 44, Issue 5, 2004, Pages 797-803

  Manessis, Dionysios ^a   Patzelt, Rainer ^a   Ostmann, Andreas ^b   Aschenbrenner, Rolf ^b   Reichl, Herbert ^b  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^b FRAUNHOFER IZM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROPLATING; GOLD PLATING; NICKEL PLATING; OPTICAL INTERCONNECTS; PARTICLE SIZE ANALYSIS; PRINTING; SILICON WAFERS; WSI CIRCUITS;

BUMPING; STENCIL PRINTING TECHNOLOGY;

FLIP CHIP DEVICES;

EID: 1842842325     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(03)00361-5     Document Type: Article

References (13)

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