Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 37, Issue 1, 2004, Pages 5-19

  Manniesing, Rashindra ^a,c   Kleihorst, Richard ^b   Van der Avoird, André ^b,d   Hendriks, Emile ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c UNIVERSITY MEDICAL CENTER UTRECHT   (Netherlands)

^d Magma Da   (Netherlands)

Author keywords

Linear processor array; Parallel processing; Power estimation; VLSI design

Indexed keywords

ALGORITHMS; CONVOLUTION; ENERGY DISSIPATION; ENERGY UTILIZATION; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

LINEAR PROCESSOR ARRAYS (LPA); PARALLEL PROCESSING; VLSI DESIGN;

SIGNAL PROCESSING;

EID: 1842689585     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000017000.91377.a7     Document Type: Article

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