VLSI parallel architecture of low density parity check decoder for turbo codes

International Symposium on IC Technology, Systems and Applications

Volumn 9, Issue , 2001, Pages 254-257

  Lee, W L ^a   Wu, Angus ^a   Li, P ^a  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DECODING; PARALLEL PROCESSING SYSTEMS; TURBO CODES;

LOW DENSITY PARITY CHECK DECODER; SEQUENTIAL DECODER;

VLSI CIRCUITS;

EID: 1842640114     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Sangjin Hong, Joonhwan Yi and Wayne E. Stark, and Implementation of Low-complexity Adaptive Turbo-code Encoder and Decoder for Wireless Mobile Communication Applications," IEEE Workshop on Signal Processing Systems, 1998, pp. 233-242.
2. Sangjin Hong and Wayne E. Stark, VLSI Circuit Complexity and Decoding Performance Analysis of Low-power RSC Turbo-code and Iterative Block Decoders Design, Proc. of the IEEE Military Communications Conf., vol. 3, 1998, pp. 708-712.
3. Guido Masera, Gianluca Piccinini, Massimo Ruo Roch and Maurizio Zamboni, VLSI Architectures for Turbo Codes, Tran. on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 3, September 1999, pp. 369-379.
4. Ping Li and W. K. Leung, "Decoding the Low Density Parity Check Code with Finite Quantization Bits," IEEE Communications Letters, vol. 4, no. 2, February 2000, pp. 62-64.
5. R. G Gallager, "Low Density Parity Check Codes," IRE Tran. on Information Theory, IT-8, 1962, pp. 21-28.