Modular multiplication for FPGA implementation of the IDEA block cipher

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2003-January, Issue , 2003, Pages 412-422

  Beuchat, Jean Luc ^a  

^a UNIVERSITÉ DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PUBLIC KEY CRYPTOGRAPHY; SECURITY OF DATA;

ARITHMETIC OPERATIONS; COMBINING OPERATIONS; EFFICIENT IMPLEMENTATION; FPGA IMPLEMENTATIONS; INTEGER MULTIPLICATIONS; MODULAR MULTIPLICATION; MULTIPLIER BLOCKS; SYMMETRIC KEY ALGORITHMS;

CRYPTOGRAPHY;

EID: 1842619314     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2003.1212864     Document Type: Conference Paper

References (19)

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