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Volumn 2002-January, Issue , 2002, Pages 253-264

Refining instruction set architecture for high-performance multimedia processing in constrained environments

Author keywords

Acceleration; Computer architecture; Discrete cosine transforms; Home appliances; Instruction sets; Kernel; Microprocessors; Modems; Scalability; Testing

Indexed keywords

ACCELERATION; COSINE TRANSFORMS; COST EFFECTIVENESS; COSTS; DISCRETE COSINE TRANSFORMS; DOMESTIC APPLIANCES; MEDIAN FILTERS; MICROPROCESSOR CHIPS; MODEMS; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; REFINING; SCALABILITY; TESTING;

EID: 84895373064     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030724     Document Type: Conference Paper
Times cited : (10)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.