Layered approach to designing system test interfaces

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 331-336

  Chiang, Man Wah ^a   Zilic, Z ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

Circuit testing; Control systems; Costs; Design methodology; Integrated circuit interconnections; Integrated circuit testing; Logic testing; Protocols; Registers; System testing

Indexed keywords

COMPLEX NETWORKS; CONTROL SYSTEMS; COSTS; DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUITS; NETWORK PROTOCOLS; SYSTEM THEORY; VLSI CIRCUITS;

CIRCUIT TESTING; DESIGN METHODOLOGY; INTEGRATED CIRCUIT INTERCONNECTIONS; LOGIC TESTING; REGISTERS; SYSTEM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 18144416085     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197671     Document Type: Conference Paper

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