A design for test technique for parametric analysis of SRAM: On-die low yield analysis

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 105-113

  Mauck, Benjamin M ^a   Ravichandran, Vishnumohan ^a   Mughal, Usman Azeez ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; NONDESTRUCTIVE EXAMINATION; STATIC RANDOM ACCESS STORAGE;

CACHE TESTING; FAULT ISOLATION; LOW YIELD ANALYSIS (LYA); PROCESS SCALING;

INTEGRATED CIRCUIT TESTING;

EID: 18144414722     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. van de Goor, A.J. "Testing Semiconductor Memories: Theory and Practice", ComTex Publishing, Verzijl Gouda, The Netherlands 1999.
2. Meixner, Anne. "Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique", IEEE International Test Conference, 1997: 1043.
3. Mulder, Randal, Sam Subramanian, Ed Widener, and Tony Chrastecky. "Improved SRAM 6T Cell Failure Analysis using MCSpice Bit Cell Defect Modeling", International Symposium for Testing and Failure Analysis, 2003: 363-370.
4. Chinnaswamy, Kumar, Ma, Lin, Pandyan, Gunjan and Chen, Wenliang. "Design of Cache LYA Access Under High Leakage Process," Intel Design and Test Technology Conference 2001.
5. www.sematec.com. March 2004.
6. Rajput, S.S and Jamuar, S.S. "Low voltage, low power, high performance current mirror for portable analogue and mixed mode application," IEEE Proc.-Circuits Devices Syst., Vol.148, No.5, October 2001: 273-278.
7. Behzad Razavi. "Design of Analog CMOS Integrated Circuits," Tata McGraw-Hill Edition 2002.
8. Gendai, Yuji, Yoshihiro Komatsu, Shinya Hirase, and Masato Kawata. "An 8b 500MHz ADC," IEEE International Solid-State Circuit Conference, 1991: 172-174.