Improved SRAM 6T Bit Cell Failure Analysis using MCSpice Bit Cell Defect Modeling

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 2003-November, Issue , 2003, Pages 363-370

  Mulder, Randal ^a   Subramanian, Sam ^a   Widener, Ed ^a   Chrastecky, Tony ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 10444244737     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.31399/asm.cp.istfa2003p0363     Document Type: Conference Paper

References (3)

1. Nagaraj P., S. Upadhyaya, K. Zarrineh and D. Adams, "Defect analysis and realistic fault model extensions for multiport SRAMs", 10th IEEE North Atlantic Test Workshop, Gloucester, MA, May 2001.
2. R. Dekker, F. Beenker and L. Thijssen, "A Realistic Fault Model and Test Algorithms for Static Random Access Memories" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 567 572, 1990.
3. M. Redeker, B. Cockburn, D. Elliott, "Fault Models and Tests for a 2-Bit-per-Cell MLDRAM", IEEE Design and Test of Computers, 199