Power reduction in test-per-scan BIST

Proceedings - 6th IEEE International On-Line Testing Workshop

Volumn , Issue , 2000, Pages 133-138

  Zhang, Xiaodong ^a   Roy, K ^b  

^a SYNOPSYS INC   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

BIST; Low Power; Low Power BIST; Test per scan; Testing; Weighted Random Pattern

Indexed keywords

BUILT-IN SELF TEST; CHAINS; RECONFIGURABLE HARDWARE; TESTING;

COMBINATIONAL BLOCKS; COMBINATIONAL LOGIC; LOW POWER; POWER REDUCTIONS; RANDOM PATTERN; SIGNAL ACTIVITY; SIGNAL TRANSITION; TEST-PER-SCAN;

ELECTRIC LOSSES;

EID: 17644362208     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2000.856625     Document Type: Conference Paper

References (13)

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