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Volumn 23, Issue 1, 1999, Pages 93-107

Scalable architecture for MPEG-4 wavelet quantization

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; STANDARDS; VECTOR QUANTIZATION; WAVELET TRANSFORMS;

EID: 17544394365     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008144820747     Document Type: Article
Times cited : (19)

References (25)
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  • 4
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  • 9
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  • 12
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  • 14
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    • The design of an adaptive on-line binary arithmetic-coding chip
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    • S. Kuang, J. Jou, and Y. Chen, "The design of an adaptive on-line binary arithmetic-coding chip," IEEE Transactions on Circuits and Systems-I, Vol. 4, No. 7, pp. 693-706, July 1998.
    • (1998) IEEE Transactions on Circuits and Systems-I , vol.4 , Issue.7 , pp. 693-706
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  • 15
    • 0028754935 scopus 로고
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    • La Jolla CA, Oct. 1994. Also in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon (Eds.), IEEE Press, New York
    • F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man, "Global communication and memory optimizing transformations for low power signal processing systems," IEEE Workshop on VLSI Signal Processing, La Jolla CA, Oct. 1994. Also in VLSI Signal Processing VII, J. Rabaey, P. Chau, and J. Eldon (Eds.), IEEE Press, New York, pp. 178-187, 1994.
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  • 16
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    • Information technology-generic coding of audio-visual objects, Part 2: Visual, ISO/IEC FDIS 14496-2 (Final Drafts International Standard)
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  • 23
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.