Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

IEEE Transactions on Electron Devices

Volumn 52, Issue 4, 2005, Pages 492-499

  Akil, Nader ^a   van Duuren, Michiel ^a   Slotboom, Michiel ^a   Baks, Wilko ^a   Goarin, Pierre ^a   van Schaijk, Rob ^a   Tello, Pablo G ^a   Cuppens, Roger ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

EEPROM; Halo; Source side injection; Technology computer aided design (TCAD)

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION; PROM;

MEMORY READOUT CURRENT; SOURCE-SIDE INJECTION; TECHNOLOGY COMPUTER AIDED DESIGN;

NONVOLATILE STORAGE;

EID: 17444384871     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.844760     Document Type: Article

References (15)

1. M. van Duuren, R. van Schaijk, N. Akil, W. Baks, P. Goarin, M. Slotboom, P. G. Tello, F. Widdershoven, and N. Wils, "Compact poly-CMP embedded Flash memory cells for one or two bit storage," in Proc. NVSMW, 2003, pp. 73-74.
2. M. Slotboom, P. Goarin, N. Akil, M. van Duuren, M. Demand, J. M. D. Wouters, S. Beckx, P. Leray, C. Baerts, N. Heylen, and I. Pollentier, "Gate isolation technology for compact poly-CMP embedded Flash memories." in Proc. ESSDERC, 2003, pp. 159-162.
3. 2PROM cell for embedded memory applications," IEEE Trans. Electron Devices. vol. 40, no. 12, pp. 2255-2263, Dec. 1993.
4. K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, "A new Flash-erase EEPROM cell with a sidewall select-gate on its source side," in IEDM Tech. Dig., 1989, pp. 603-306.
5. P. Goarin, R. van Schaijk, M. Slotboom, P. G. Tello, M. van Duuren, N. Akil, and W. Baks, "Self-aligned access gate technology for compact embedded Flash memories," Proc. ESSDERC, 2004, pp. 281-284.
6. J. van Houdt, P. Hermans, L. Deferm, G. Groeseneken, and H. E. Maes, "Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications," IEEE Trans. Electron Devices, vol. 39, no. 5, pp. 1150-1156, May 1992.
7. "TSUPREM-4 User's Manual," Synopsys, Inc., 2002.4.0, 2002.
8. "MEDICI User's Manual," Synopsys, Inc., 2002.4.0, 2002.
9. T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi, and M. Bohr, "Asymetric source/drain extension transistor structure for high performance sub-50-nm gate length CMOS devices," in Symp. VLSI Tech. Dig., 2001, pp. 17-18.
10. C. R. Huster and C. Riccobene, "Asymmetric retrograde halo metal - oxide - semiconductor field-effect transistor (MOSFET)," U.S. Patent 6 667 512 B1, Dec. 23, 2003.
11. Y. Zhang, J. Wan, K. L. Wang, and B. Y. Nguyen, "Design of 10-nm-scale recesses asymmetric Schottky barrier MOSFETs," IEEE Electron Device Lett., vol. 23, no. 7, pp. 419-421, Jul. 2002.
12. S. J. Ahn, G. T. Jung, C. H. Cho, S. H. Shin, J. Y. Lee, J. G. Lee, H. S. Jeong, and K. Kinam, "Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics," in Symp. VLSI Tech. Dig., 2002, pp. 176-177.
13. S.-H. Kim and K. Do, "Nonvolatile memory device having asymmetric source/drain region and fabricating method thereof," U.S. Patent 20 040 080 012 A1, Apr. 29, 2004.
14. J. van Houdt, G. Groeseneken, and H. E. Maes, "An analytical model for the optimization of source-side injection Flash EEPROM devices," IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1314-1320, Jul. 1995.
15. D. Dormans, D. Boter, A. Cacciato, M. Diekema, C. Dijkstra, M. Hendriks, R. van der Linde, G. Tao, H. Valk, E. van der Vegt, and R. Verhaar, "Low-voltage embedded Flash-EEPROM in 0.18-μm CMOS," in Proc. SSDM, 2001, pp. 540-541.