On-chip crosstalk mitigation for densely packed differential striplines using via fence enclosures

Electronics Letters

Volumn 41, Issue 7, 2005, Pages 412-414

  Guckenberger, D ^a   Schuster, C ^b   Kwark, Y ^b   Kornegay, K ^a  

^a School of Operations Research and Industrial Engineering   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; CROSSTALK; DIGITAL INTEGRATED CIRCUITS; ELECTRIC LINES; FREQUENCIES; OPTIMIZATION;

DIFFERENTIAL CROSSTALK; DIFFERENTIALL STRIPLINES; ISOLATION; ON-CHIP CROSSTALK;

STRIP TELECOMMUNICATION LINES;

EID: 17444379646     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20058423     Document Type: Article

References (4)

1. Ponchak, G., Chen, D., Yook, J.-G., and Katehi, L.: 'Characterization of plated via hole fences for isolation between stripline circuits in LTCC packages'. 1998 IEEE IMS Dig., Baltimore, MD, USA, June 1998, Vol. 3, pp. 1831-1834
2. Ponchak, G., Chun, D., Yook, J.-G., and Katehi, L.: 'The use of metal filled via holes for improving isolation in LTCC RF and wireless multichip packages', IEEE Trans. Adv. Packag., 2000, 23, (1), pp. 88-99
3. Gipprich, J., and Stevens, D.: 'A new via fence structure for crosstalk reduction in high density stripline packages'. 2001 IEEE IMS Dig., Phoenix, AZ, USA, June 2001, Vol. 3, pp. 1719-1722
4. Janezic, M., and Jargon, J.: 'Complex permittivity determination from propagation constant measurements', IEEE Microw. Guid. Wave Lett., 1999, 9, (2), pp. 76-78