메뉴 건너뛰기





Volumn 3, Issue , 1998, Pages 1831-1834

Characterization of plated via hole fences for isolation between stripline circuits in LTCC packages

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COUPLED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTROMAGNETIC WAVES; FINITE ELEMENT METHOD;

EID: 0031638396     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (29)

References (3)
  • Reference 정보가 존재하지 않습니다.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.