Modeling of high-current source-gated transistors in amorphous silicon

Applied Physics Letters

Volumn 86, Issue 7, 2005, Pages 1-3

  Balon, F ^a   Shannon, J M ^a   Sealy, B J ^a  

^a UNIVERSITY OF SURREY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; CAPACITANCE; COMPUTER SIMULATION; ELECTRON EMISSION; ION IMPLANTATION; LIGHT EMITTING DIODES; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR INSULATOR BOUNDARIES; TRANSCONDUCTANCE;

GATE VOLTAGE; REVERSE BIASED BARRIERS; SOURCE GATED TRANSISTORS (SGT); THERMIONIC FIELD EMISSION;

FIELD EFFECT TRANSISTORS;

EID: 17044438287     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1865348     Document Type: Article

References (5)

1. J. M. Shannon and E. G. Gerstner, IEEE Electron Device Lett. 24, 405 (2003).
2. J. M. Shannon and E. G. Gerstner, Solid-State Electron. 48, 1155 (2004).
3. J. M. Shannon, Appl. Phys. Lett. 85, 326 (2004).
4. K. J. B. M. Nieuwesteeg, M. van der Veen, T. J. Vink, and J. M. Shannon, J. Appl. Phys. 74, 2581 (1993).
5. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. (Wiley Interscience, New York, 1981), Chap.