Modular and scalable architecture for the realization of high-speed programmable rank order filters using threshold logic

VLSI Design

Volumn 11, Issue 2, 2000, Pages 115-128

  Hatirnaz, I ^a,b,c   Gurkaynak F K ^a,b,d   Leblebici, Y ^a,b,d,e,f  

^a Worcester Polytechnic Institute   (United States)

^b ISTANBUL TECHNICAL UNIVERSITY   (Turkey)

^c Marmara Research Institute   (Turkey)

^d EPFL   (Switzerland)

^e UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^f UIUC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; INTEGRATED CIRCUIT LAYOUT; THRESHOLD LOGIC;

CAPACITIVE THRESHOLD LOGIC (CTL) GATES; HIGH-SPEED PROGRAMMABLE RANK ORDER FILTERS; MULTI-INPUT PROGRAMMABLE MAJORITY FUNCTIONS;

VLSI CIRCUITS;

EID: 1642617993     PISSN: 1065514X     EISSN: None     Source Type: None    
DOI: 10.1155/2000/98945     Document Type: Article

References (12)

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