A binary logic synthesis approach to the bit-level implementation of generalized rank-order filters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1992, Pages 109-112

  Gu, Qunshan ^a   Swamy, M N S ^a  

^a Dept of Electrical and Computer Engineering   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; CODES (SYMBOLS); COMPUTER CIRCUITS; LOGIC SYNTHESIS;

BUILDING BLOCKES; COMBINATIONAL LOGIC CIRCUITS; DATA WINDOWS; PIPELINED ARCHITECTURE; PROPOSED ARCHITECTURES; RANK-ORDER FILTERS; THRESHOLD DECOMPOSITION; VLSI IMPLEMENTATION;

PASSIVE FILTERS;

EID: 85067203808     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230002     Document Type: Conference Paper

References (7)

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