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Volumn 3, Issue , 2003, Pages 1179-1185

Comparing multiported cache schemes

Author keywords

Cache memories; Computer architecture; Multibanked caches; Multiported caches

Indexed keywords

COMPUTER ARCHITECTURE; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; SYSTEMS ANALYSIS; TIME DIVISION MULTIPLEXING;

EID: 1642278870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (11)
  • 1
    • 0035390811 scopus 로고    scopus 로고
    • A high bandwidth memory pipeline for a wide issue processors
    • July
    • S. Cho, P. C. Yew and G. Lee. A high bandwidth memory pipeline for a wide issue processors, IEEE Transactions on Computers, Vol. 50, No. 7, July 2001, p. 706-723.
    • (2001) IEEE Transactions on Computers , vol.50 , Issue.7 , pp. 706-723
    • Cho, S.1    Yew, P.C.2    Lee, G.3
  • 3
    • 0032639289 scopus 로고    scopus 로고
    • The alpha 21264 microprocessor
    • March-April
    • R.E. Kessler, The Alpha 21264 Microprocessor. IEEE Micro, March-April 1999, p. 24-36.
    • (1999) IEEE Micro , pp. 24-36
    • Kessler, R.E.1
  • 4
    • 0003946111 scopus 로고    scopus 로고
    • Cacti 2.0: An integrated cache timing and power model
    • Research Report Western Research Lab 1999
    • G. Reinman and N. Jouppi. Cacti 2.0: An Integrated Cache Timing and Power Model, Research Report Western Research Lab 1999.
    • Reinman, G.1    Jouppi, N.2
  • 6
    • 0003450887 scopus 로고    scopus 로고
    • CACTI 3.0: An integrated cache timing, power, and area model
    • Research Report Western Research Lab 2001/2, August
    • P. Shivakumar and N. P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model, Research Report Western Research Lab 2001/2, August 2001.
    • (2001)
    • Shivakumar, P.1    Jouppi, N.P.2
  • 9
    • 0003650381 scopus 로고
    • An enhanced access and cycle time model for on-chip caches
    • Research Report Western Research Lab, 93/5, July
    • S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches. Research Report Western Research Lab, 93/5, July 1994.
    • (1994)
    • Wilton, S.1    Jouppi, N.2
  • 10
    • 0003158656 scopus 로고
    • Hitting the memory Wall: Implications of the obvious
    • March
    • W. Wulf and S. McKee. Hitting the Memory Wall: Implications of the Obvious. Computer Architecture News, 23(1):20-24, March 1995.
    • (1995) Computer Architecture News , vol.23 , Issue.1 , pp. 20-24
    • Wulf, W.1    McKee, S.2
  • 11
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor
    • March-April
    • K. C. Yeager, The MIPS R10000 superscalar microprocessor. IEEE Micro, March-April 1996.
    • (1996) IEEE Micro
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.