Design and implementation of a high speed microprocessor simulator BurstScalar

Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS

Volumn , Issue , 2004, Pages 364-372

  Nakada, Takashi ^a   Nakashima, Hiroshi ^a  

^a TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROARCHITECTURAL SIMULATION; MICROARCHITECTURAL STATE; MICROPROCESSOR SIMULATOR; TRANSITION TABLE;

BENCHMARKING; COMPUTER SIMULATION; DATA REDUCTION; ENCODING (SYMBOLS); ITERATIVE METHODS; RESEARCH AND DEVELOPMENT MANAGEMENT; SCHEDULING;

MICROPROCESSOR CHIPS;

EID: 16244415884     PISSN: 15267539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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