M-Trie: An efficient approach to on-chip logic minimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 428-435

  Ahmad, Seraj ^a   Mahapatra, Rabi ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC MINIMIZATION; LOGIC SYNTHESIS; MINIMIZATION PROBLEM; NETWORK PROCESSORS;

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; MICROPROCESSOR CHIPS; OPTIMIZATION; PROBLEM SOLVING; PROGRAM PROCESSORS; RESOURCE ALLOCATION;

LOGIC PROGRAMMING;

EID: 16244405886     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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