Dynamic-Vt, dual-power-supply SRAM cell using D2G-SOI for low-power SoC application

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 109-111

  Yamaoka, Masanao ^a   Osada, Kenichi ^a   Itoh, Kiyoo ^a   Tsuchiya, Ryuta ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; EMBEDDED SYSTEMS; ERROR ANALYSIS; MOSFET DEVICES; SEMICONDUCTOR DIODES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

BIT-LINE (BL); SOFT-ERROR RATE (SER); STATIC-NOISE MARGIN (SNM); SYSTEM ON CHIP (SOI);

STATIC RANDOM ACCESS STORAGE;

EID: 16244373003     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. Nakagome et al., "Review and future prospects of low-voltage RAM circuits," IBM Journal of Research and Development, pp. 525-552, vol. 47, No. 5/6, 2003
2. E. Seevinck et al., "Static-Noise Margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, Vol, SC-22, No. 5, Oct. 1987.
3. T. Hiramoto et al., "Low-Power Device Design of Fully-Depleted SOI MOSFETs," Semiconductor Device Research Symposium,
4. K. Itoh et al., "A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load", Symposium on VLSI Circuits Digest of Technical Papers, pp 132-133, June 1996.
5. M. Yamaoka et al., "0.4-V Logic Library Friendly SRAM Array Using Rectangular-Diffusion Cell and Delta-Boosted-Array-Voltage Scheme," Symposium on VLSI circuit Digest of Technical Papers, pp. 170-173, June 2002.
6. M. Yamaoka et al., "Low-Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology," Symposium on VLSI circuit Digest of Technical Papers, pp. 288-291, June 2004.