Use of symbolic performance models in layout-inclusive RF low noise amplifier synthesis

BMAS 2004 - Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference

Volumn , Issue , 2004, Pages 130-134

  Ranjan, Mukesh ^a   Bhaduri, Amitava ^a   Verhaegen, Wim ^b   Mukherjee, Bhaskar ^c   Vemuri, Ranga ^a   Gielen, Georges ^b   Pacelli, Andrea ^c  

^a University of Cincinnati   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CODES (SYMBOLS); INTERCONNECTION NETWORKS; LOGIC PROGRAMMING; NONLINEAR SYSTEMS; PARAMETER ESTIMATION; PROGRAM COMPILERS;

LAYOUT GENERATORS; LAYOUT-IN-LOOP SYNTHESIS; LOW NOISE AMPLIFIERS (LNA); SYMBOLIC PERFORMANCE MODELS (SPM);

AUDIO FREQUENCY AMPLIFIERS;

EID: 15944413777     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. A. Bhadhuri et al., ""Parasitic-Aware Synthesis of RF LNA Circuits considering Quasi-Static Extraction of Inductors and Interconnects"," in Proc. of MWSCAS (Accepted to appear), July 2004.
2. A. E. Ruehli and A. C. Cangellaris, ""Progress in the Methodologies for the Electrical Modeling of Interconnects and Electronic Packages," in Proc. IEEE, May 2001, pp. 740-771.
3. A. Pacelli, ""A local circuit topology for inductive parasitics"," in Proc. of ICCAD, Nov. 2002, pp. 208-214.
4. C. De Ranter et al., ""CYCLONE: Automated Design and Layout of RF LC-Oscillators"," in Proc. of DAC, June 2000, pp. 11-14.
5. M. del Mar Hershenson et al., ""Design and optimization of LC oscillators"," in Proc. of ICCAD, 1999.
6. G. Gielen and R. Rutenbar, ""Computer-Aided Design of Analog and mixed-signal integrated circuits"," Proc. IEEE, vol. 88, no. 12, pp. 1825-1854, Dec. 2000.
7. G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer Academic Publishers, 1991.
8. H. Sampath and R. Vemuri, ""MSL: A High-Level Language for Parameterized Analog and Mixed-Signal Layout Generators"," in Proc. of IFIP 12th Intl. Conf. on VLSI, 2003.
9. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 2002.
10. M.Ranjan et al., ""Fast, Layout-Inclusive Analog Circuit Synthesis using pre-compiled parasitic-aware symbolic performance models"," in Proc. of DATE, Feb 2004, pp. 604-309.
11. P. Vancorenland, G. Van der Plas, M. Steyaert, G. Gielen and W. Sansen, ""A Layout-aware Synthesis Methodology for RF Circuits"," in Proc. of ICCAD, 2001.
12. R. Gupta, B. M. Ballweber and D. J. Allstot, ""Design and Optimization of CMOS RF Power Amplifiers"," in IEEE JSSC, 2001, pp. 166-175.
13. C.-J. R. Shi and X.-D. Tan, ""Compact Representation and Efficient Generation of s-Expanded Symbolic Network Functions for Computer-Aided Analog Circuit Design"," IEEE Trans. on CAD of Integrated Circuits and System, vol. 20, no. 7, pp. 813-827, July 2001.
14. X.-D. Tan and C.-J. R. Shi, ""Symbolic circuit-noise analysis and modeling with determinant decision diagrams"," in Proc. of ASP-DAC, Yokohama, Japan, Jan. 25-28, 2000, pp. 283-287.
15. W. Verhaegen and G. Gielen, ""Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits"," in Proc. of DAC, 2001, pp. 139-144.
16. P. Wambacq, G. Gielen, P. Kinget, and W.Sansen, ""High- frequency distortion analysis of analog integrated circuits"," IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 3, pp. 335-345, Mar. 1999.