A Selected Area Planar Tem (SAPTEM) Sample Preparation Procedure for Failure Analysis of Integrated Circuits

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 1998, Pages 131-135

  Subramanian, S ^a   Schani, P ^a   Widener, E ^a   Liston, P ^a   Moss, J ^a   Soorholtz, V ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST STATIC RANDOM ACCESS MEMORIES (FSRAM); SELECTED AREA PLANAR TRANSMISSION ELECTRON MICROSCOPY (SAPTEM);

DISLOCATIONS (CRYSTALS); ETCHING; GRINDING (MACHINING); INTEGRATED CIRCUITS; MILLING (MACHINING); SURFACE REACTIONS; THICKNESS MEASUREMENT; TRANSMISSION ELECTRON MICROSCOPY;

FAILURE ANALYSIS;

EID: 1542360801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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4. S. Leslie, K. L. Pey, K. S. Sim, M. T. F. Beh and G. P. Goh, Proceedings of the 21st International Symposium for Testing and Failure Analysis (ISTFA-95), 353-362 (1995).
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