New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 168-171

  Das, K K ^a   Joshi, R V ^b   Chuang, Ching Te ^b   Cook, P W ^b   Brown, R B ^a  

^a University of Michigan   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuit noise; Contact resistance; Immune system; Noise reduction; Permission; Stacking; Switches; Switching circuits; Transistors; Very large scale integration

Indexed keywords

CHOPPERS (CIRCUITS); CONTACT RESISTANCE; DESIGN; IMMUNE SYSTEM; LOW POWER ELECTRONICS; NANOTECHNOLOGY; NOISE ABATEMENT; POWER ELECTRONICS; SWITCHES; SWITCHING CIRCUITS; TRANSISTORS; VLSI CIRCUITS;

CIRCUIT NOISE; DESIGN CONSTRAINTS; PERMISSION; SIMULTANEOUS REDUCTION; STACKING; STAND-BY LEAKAGE; SUB-THRESHOLD LEAKAGE; ULTRA LOW LEAKAGES;

ELECTRIC NETWORK ANALYSIS;

EID: 1542329231     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231855     Document Type: Conference Paper

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