Novel ultra low-leakage power circuit techniques and design algorithms in PD-SOI for sub-1 V applications

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 88-90

  Das, Koushik K ^a   Brown, Richard B ^a  

^a University of Michigan   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; SEMICONDUCTOR SWITCHES; TRANSISTORS;

POWER CIRCUIT DESIGN;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036458770     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044429     Document Type: Conference Paper

References (7)

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3. H. Kawaguchi, et al., IEEE Journal of Solid-State Circuits (JSSC), Oct. 2000, pp. 1498-1501.
4. M. Casu and G. Piccinini, ISLPED '01, pp. 287-290.
5. Siva Narendra, et al., ISLPED 2001, pp. 195-200.
6. S.V. Kosonocky, et al., ISLPED 2001, pp. 165-169.
7. S. Mutoh, et al., ASP-DAC 1999, pp. 113-116.