Scalable hardware memory disambiguation for HIGH-ILP processors

IEEE Micro

Volumn 24, Issue 6, 2004, Pages 118-127

  Sethumadhavan, Simha ^a   Desikan, Rajagopalan ^b   Burger, Doug ^a   Moore, Charles R ^a   Keckler, Stephen W ^a  

^a University of Texas at Austin   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; OPTIMIZATION; RANDOM ACCESS STORAGE;

INSTRUCTION LEVEL PARALLELISM PROCESSORS; LOAD-STORE QUEUE; MEMORY DISAMBIGUATION; OUT-OF-ORDER ARCHITECTURE;

DATA STORAGE EQUIPMENT;

EID: 15044365237     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.87     Document Type: Article

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