Opportunities and challenges for high-k gate dielectrics

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2004, Pages 1-4

  Ma, T P ^a  

^a Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC DEVICES; ELECTRODES; ELECTRON MOBILITY; ELECTRON TUNNELING; FERMI LEVEL; GRAIN SIZE AND SHAPE; HAFNIUM COMPOUNDS; INTERFACES (MATERIALS); LEAKAGE CURRENTS; MOSFET DEVICES; PHONONS; RESEARCH AND DEVELOPMENT MANAGEMENT; SILICA; THERMODYNAMIC STABILITY;

ELECTRONIC TRAPS; EQUIVALENT OXIDE THICKNESS (EOT); HIGH-K DIELECTRIC TECHNOLOGY; INELASTIC ELECTRON TUNNELING SPECTROSCOPY (IETS);

GATES (TRANSISTOR);

EID: 14844312078     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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12. 2 / A12O3 Gate Stacks with TiN Electrodes", IEEE Trans. on ED, Vol. 50, No. 5, pp. 1261 - 1269, (2003).