SCOPUS 정보 검색 플랫폼

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 1-4

An investigation into transistor-based adiabatic logic styles

(2) Arsalan, Muhammad a Shams, Maitham a

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CIRCUITS; ELECTRIC INVERTERS; ELECTRIC LOADS; ENERGY DISSIPATION; ENERGY UTILIZATION; FEEDBACK; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION; SIGNAL PROCESSING; STANDARDS; SWITCHING CIRCUITS;

ADIABATIC LOGIC STYLES; CHARGE RECOVERY; ENERGY SAVINGS; LOW-POWER SYSTEMS;

TRANSISTORS;

EID: 14844294813 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (7)

References (7)

1
- 1642369164
- Common mistakes in adiabatic logic design and how to avoid them
- M. P. Frank, "Common Mistakes in Adiabatic Logic Design and How to Avoid Them," Proceedings of International Workshop on Methodologies in Low-Power Design 2003.
- Proceedings of International Workshop on Methodologies in Low-power Design 2003
- Frank, M.P.¹

2
- 0029194994
- 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
- A. Krame, J.S.Denker, B.Flower, J. Moroney: "2nd Order Adiabatic Computation with 2N-2P and 2N-2N2P logic circuits", Int. Symposium on Low Power Design, pp. 191-196, 1995.
- (1995) Int. Symposium on Low Power Design , pp. 191-196
- Krame, A.¹ Denker, J.S.² Flower, B.³ Moroney, J.⁴

3
- 23044533221
- Designing carry look-ahead adders with an adiabatic logic standard-cell library
- A. Blotti, M. Castellucci, R. Saletti; "Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library"; PATMOS 2002, pp. 118-127, 2002.
- (2002) PATMOS 2002 , pp. 118-127
- Blotti, A.¹ Castellucci, M.² Saletti, R.³

4
- 0031258473
- Pass-transistor adiabatic logic using single power-clock supply
- Oct
- V.G. Oklobdzija, D. Maksimovic, Fengcheng Lin;"Pass-transistor adiabatic logic using single power-clock supply" Processing, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal, Vol: 44 Issue: 10, Page(s): 842-846. Oct 1997.
- (1997) Processing, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal , vol.44 , Issue.10 , pp. 842-846
- Oklobdzija, V.G.¹ Maksimovic, D.² Lin, F.³

5
- 0034244994
- Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
- Aug
- D. Maksimovic, V.G. Oklobdzija, B. Nikolic, K.W. Current, "Clocked CMOS adiabatic logic with integrated single-phase power-clock supply", IEEE Transactions on VLSI Systems, Volume: 8 Issue: 4, pp 460-463, Aug 2000.
- (2000) IEEE Transactions on VLSI Systems , vol.8 , Issue.4 , pp. 460-463
- Maksimovic, D.¹ Oklobdzija, V.G.² Nikolic, B.³ Current, K.W.⁴

6
- 0034776735
- An improved pass-gate adiabatic logic
- L. Varga, F. Kovacs, G. Hosszu, "An improved pass-gate adiabatic logic", Proceedings. 14th Annual IEEE International, ASIC/SOC Conference, pp 208-211 2001.
- (2001) Proceedings. 14th Annual IEEE International, ASIC/SOC Conference , pp. 208-211
- Varga, L.¹ Kovacs, F.² Hosszu, G.³

7
- 0030125320
- An efficient charge recovery logic circuit
- April
- Y. Moon; D. K. Jeong, "An efficient Charge Recovery Logic Circuit", IEEE Journal of Solid-State Circuites, Vol 31, No. 4. pp. 514-522, April 1996.
- (1996) IEEE Journal of Solid-state Circuites , vol.31 , Issue.4 , pp. 514-522
- Moon, Y.¹ Jeong, D.K.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.