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Volumn , Issue , 2004, Pages 337-339

Design of reconfigurable general finite field multiplier in GF(2 m)

Author keywords

Canonical basis; Encryption; Finite Field Multiplication; Normal basis; VLSI

Indexed keywords

CRYPTOGRAPHY; GATES (TRANSISTOR); POLYNOMIALS; PRINCIPAL COMPONENT ANALYSIS; SET THEORY; SIGNAL ENCODING; SIGNAL PROCESSING; VLSI CIRCUITS;

EID: 14844292645     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (7)
  • 3
    • 0020207091 scopus 로고
    • Bit-serial reed-solomon encoders
    • Nov.
    • E. R. Berlekamp, "Bit-serial Reed-Solomon encoders," IEEE Trans. Inform. Theory, Vol. IT-28, pp. 869-874, Nov. 1982.
    • (1982) IEEE Trans. Inform. Theory , vol.IT-28 , pp. 869-874
    • Berlekamp, E.R.1
  • 5
    • 0032115233 scopus 로고    scopus 로고
    • Low-energy digit-serial/parallel finite field multipliers
    • L. Song, K. Parhi, "Low-Energy Digit-Serial/Parallel Finite Field Multipliers," Journal of VLSI Signal Processing, Vol. 19, pp. 149-166, 1998
    • (1998) Journal of VLSI Signal Processing , vol.19 , pp. 149-166
    • Song, L.1    Parhi, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.