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Volumn 49, Issue 10, 2000, Pages 1064-1073

VLSI algorithms, architectures, and implementation of a versatile GF(2 m) processor

Author keywords

[No Author keywords available]

Indexed keywords

CANONICAL BASIS; CRYPTOGRAPHIC PROCESSOR; DATAPATH; GALOIS FIELD PROCESSOR; TRIANGULAR BASIS;

EID: 0034291490     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.888042     Document Type: Article
Times cited : (20)

References (22)
  • 1
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    • Credits and Debits on the Internet
    • Feb.
    • M.A. Sirbu, "Credits and Debits on the Internet," IEEE Spectrum, vol. 34, no. 2, pp. 23-29, Feb. 1997.
    • (1997) IEEE Spectrum , vol.34 , Issue.2 , pp. 23-29
    • Sirbu, M.A.1
  • 2
    • 0031075920 scopus 로고    scopus 로고
    • In Your Pocket: Smartcards
    • Feb.
    • C.H. Fancher, "In Your Pocket: Smartcards," IEEE Spectrum, vol. 34, no. 2, pp. 47-53, Feb. 1997.
    • (1997) IEEE Spectrum , vol.34 , Issue.2 , pp. 47-53
    • Fancher, C.H.1
  • 5
    • 0030167965 scopus 로고    scopus 로고
    • Cryptographic Smart Cards
    • June
    • D. Naccache and D. M'Raihi, "Cryptographic Smart Cards," IEEE Micro, vol. 16, no. 3, pp. 14-24, June 1996.
    • (1996) IEEE Micro , vol.16 , Issue.3 , pp. 14-24
    • Naccache, D.1    M'Raihi, D.2
  • 6
    • 0030169455 scopus 로고    scopus 로고
    • SCALPS: Smart Card for Limited Payment Systems
    • June
    • J.-F. Dhem, D. Veithen, and J.-J. Quisquater, "SCALPS: Smart Card for Limited Payment Systems," IEEE Micro, vol. 16, no. 3, pp. 42-51, June 1996.
    • (1996) IEEE Micro , vol.16 , Issue.3 , pp. 42-51
    • Dhem, J.-F.1    Veithen, D.2    Quisquater, J.-J.3
  • 11
    • 0029343883 scopus 로고
    • Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder
    • July
    • M.A. Hasan and V.K. Bhargava, "Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder," IEEE Trans. Computers, vol. 44, no. 7, pp. 938-942, July 1995.
    • (1995) IEEE Trans. Computers , vol.44 , Issue.7 , pp. 938-942
    • Hasan, M.A.1    Bhargava, V.K.2
  • 15
    • 0029344158 scopus 로고
    • Parallel Implementation of the Schur Berlekamp-Massey Algorithm on a Linearly Connected Processor Array
    • July
    • C.J. Zarowski, "Parallel Implementation of the Schur Berlekamp-Massey Algorithm on a Linearly Connected Processor Array," IEEE Trans. Computers, vol. 44, no. 7, pp. 930-933, July 1995.
    • (1995) IEEE Trans. Computers , vol.44 , Issue.7 , pp. 930-933
    • Zarowski, C.J.1
  • 17
    • 0032139059 scopus 로고    scopus 로고
    • Table of Low-Weight Binary Irreducible Polynomials
    • Hewlett-Packard Laboratories, Palo Alto, Calif., Aug.
    • G. Seroussi, "Table of Low-Weight Binary Irreducible Polynomials," Technical Report HPL-98-135, Hewlett-Packard Laboratories, Palo Alto, Calif., Aug. 1998. http://www.hpl.hp.com/ techreports/98/HPL-98-135.html.
    • (1998) Technical Report HPL-98-135
    • Seroussi, G.1
  • 18
  • 19
    • 33749982564 scopus 로고    scopus 로고
    • A Variable Dimension Galois Field Coprocessor with a Double-Bases Approach
    • Univ. of Waterloo, Canada
    • M.A. Hasan and A.G. Wassal, "A Variable Dimension Galois Field Coprocessor with a Double-Bases Approach," Technical Report E&CE no. 2000-03, Univ. of Waterloo, Canada, 2000.
    • (2000) Technical Report E&CE No. 2000-03
    • Hasan, M.A.1    Wassal, A.G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.