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Volumn , Issue , 2004, Pages 165-170

Re-configurable parallel stream processor with self-assembling and self-restorable micro-architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; OPTIMIZATION; SELF ASSEMBLY; VIRTUAL REALITY;

EID: 13944255775     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (8)
  • 3
    • 84893641728 scopus 로고    scopus 로고
    • A decade of reconfigurable computing: A visionary retrospective
    • R. Hartenstein, "A Decade of Reconfigurable Computing: a Visionary Retrospective", In Design, Automation and Test in Europe, pp. 642-649, 2001
    • (2001) Design, Automation and Test in Europe , pp. 642-649
    • Hartenstein, R.1
  • 7
    • 84949894997 scopus 로고    scopus 로고
    • Architecture-to-task optimization system (ATOS) for parallel multi-mode data-flow architectures on a base of a partially re-configurable computing platform
    • Warsaw, September
    • L. Kirischian, L. Szajek, F. Chayab, "Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Re-configurable Computing Platform", in Proc. PARELEC 2002 International Conference on Parallel Computing in Electrical Engineering, Warsaw, September 2002.
    • (2002) Proc. PARELEC 2002 International Conference on Parallel Computing in Electrical Engineering
    • Kirischian, L.1    Szajek, L.2    Chayab, F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.