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Proceedings - International Conference on Parallel Computing in Electrical Engineering, PARELEC 2002

Volumn , Issue , 2002, Pages 27-32

Architecture-to-task optimization system (ATOS) for parallel multi-mode data-flow architectures on a base of a partially reconfigurable computing platform

(3) Chayab, F a Kirischian, L a Szajek, L a

a UNIVERSITY OF VICTORIA (Canada)

Author keywords

automated synthesis; data flow applications; DFG; FPGA; optimization; Parallel architecture; partial reconfiguration

Indexed keywords

AUTOMATION; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; DATA FLOW GRAPHS; DATA TRANSFER; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOW GRAPHS; GRAPHIC METHODS; OPTIMIZATION; RECONFIGURABLE ARCHITECTURES; SYNTHESIS (CHEMICAL);

AUTOMATED SYNTHESIS; DATA FLOW; DFG; EMBEDDED COMPUTING SYSTEM; PARALLEL PROCESSING ARCHITECTURES; PARTIAL RECONFIGURATION; PERFORMANCE MEASUREMENTS; RECONFIGURABLE COMPUTING;

PARALLEL ARCHITECTURES;

EID: 84949894997 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/PCEE.2002.1115192 Document Type: Conference Paper

Times cited : (2)

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2
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- Kirischian, L.¹

3
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- Schreiber, R.¹

5
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- Automatic hardware synthesis for hybrid reconfigurable CPU featuring philips CPLDs
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6
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.