Die counting algorithm for yield modeling and die per wafer optimization

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3216, Issue , 1997, Pages 186-196

  Croft, Gregg D ^a   Lomenick, Robert L ^a   Youngblood, Douglas L ^a   Johnston, Jeffrey M ^a  

^a INTERSIL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LAYOUTS; COMPUTER ALGORITHMS; CYCLE TIMES; WAFER YIELDS; YIELD MODELS;

ALGORITHMS; DIES; FAILURE ANALYSIS; QUALITY ASSURANCE; RELIABILITY ANALYSIS; SAFETY FACTOR;

RELIABILITY;

EID: 13844270713     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.284701     Document Type: Conference Paper

References (5)

1. B.T. Murphy, "Cost-size optima of monolithic integrated circuits", Proc. IEEE, 52, pp. 1537-1545, 1964
2. C.N. Berglund, "A Unified Yield Model Incorporating Both Defect and Parametric Effects,", IEEE Transactions on Semiconductor Manufacturing, 9, 3, pp. 447-454, 1996
3. A.V. Ferris-Prabhu, "Role of Defect Size Distribution in Yield Modeling", IEEE Transactions on Electron Devices, ED-32, 9, pp. 1727-1736, 1985
4. W. Maly, H.T. Heineken, F. Agricola, "A Simple New Yield Model" Semiconductor International, pp. 148-150 July 1994
5. J. Von Bank, "An Alternate Integrated-Circuit Yield Model" IEEE Transactions on Reliability, R-35, 4, pp. 385-390 1986