A new flash memory sense amplifier in 0.18μm CMOS technology

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 941-944

  Chrisanthopoulos, A ^a   Moisiadis, Y ^b,c   Varagis, A ^a   Tsiatouhas, Y ^a   Arapoyanni, A ^b  

^a Integrated Systems Development SA   (Greece)

^b UNIVERSITY OF ATHENS   (Greece)

^c INSTITUTE OF MICROELECTRONICS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENCY; BIT LINES; BITLINE CAPACITANCE; CMOS TECHNOLOGY; CURRENT SENSING; DELAY TIME; FAST RESPONSE; HIGH TEMPERATURE SIMULATIONS; LAYOUT DESIGNS; OPERATING CONDITION; PRE-CHARGE; READ OPERATION; SENSE AMPLIFIER; SENSING SCHEMES; SILICON AREA; SIMULATION RESULT; WORST CASE;

CMOS INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

FLASH MEMORY;

EID: 13444296772     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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