An n-Well CMOS Dynamic RAM

IEEE Transactions on Electron Devices

Volumn 29, Issue 4, 1982, Pages 714-718

  Shimohigashi, Katsuhiro ^a   Masuda, Hiroo ^a   Kamigaki, Yoshiaki ^a   Itoh, Kiyoo ^a   Hashimoto, Norikazu ^a   Arai, Eisuke ^b  

^a HITACHI LTD   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

RAM;

SEMICONDUCTOR DEVICES, MOS;

DATA STORAGE, SEMICONDUCTOR;

EID: 0020113468     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1982.20767     Document Type: Article

References (14)

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3. H. Masuda et al., “A 5 V-only 64K dynamic RAM based on high S/N design,” IEEE J. Solid-State Circuits, vol. SC-15, no. 5, Oct. 1980.
4. I. Lee, et al., “A 64 kbit MOS RAM,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., p. 146, Feb. 1979.
5. K. Natori et al., “A 64 kbit MOS dynamic random access memory,” IEEE J. Solid-State Circuits, vol. SC-14, p. 482, 1979.
6. T. C. May and M. H. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-26, no. 1, p. 2, Jan. 1979.
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8. See, for example, R. H. Crawford, MOSFET in Circuit Design. New York: McGraw-Hill, 1967, p. 78.
9. K. Shimohigashi et al., “An n-well CMOS dynamic RAM,” in IEEE Electron Devices Meet. Tech. Dig., p. 835, Dec. 1980.
10. Y. Kamigaki et al., “Substrate current of MOS transistor,” in 40th Conf. Applied Physics Japan Tech. Dig., p. 457, 1979.
11. J. G. Posa, “What to expect next: A special report,” Electronics, p. 119, May 22, 1980.
12. C. A. Lee et al., “Ionization rates of holes and electrons in silicon,” Phys. Rev., p. 134, A761, 1964.
13. D. S. Yaney et al., “Alpha-particle tracks in silicon and their effect on dynamic MOS RAM reliability,” IEEE Trans. Electron Devices, vol. ED-26, no. 1, Jan. 1979.
14. R. Pashley et al., “A high performance 4K static RAM fabricated with an advanced MOS technology,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., p. 22, Feb. 1977.