A parallel architecture for secure FPGA symmetric encryption

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 1803-1810

  Swankoski, E J ^a   Brooks, R R ^a   Narayanan, V ^b   Kandemir, M ^b   Irwin, M J ^b  

^a Applied Research Laboratory   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-PERFORMANCE METHODS; KEY BLOCK CIPHERS; RANDOM FUNCTIONS; TEMPORAL ISOLATION;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; CRYPTOGRAPHY; PARALLEL PROCESSING SYSTEMS; SECURITY SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 12444292161     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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