A Quantitative Analysis of Tile Size Selection Algorithms

Journal of Supercomputing

Volumn 27, Issue 3, 2004, Pages 279-294

  Hsu, Chung Hsing ^a   Kremer, Ulrich ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

Array padding; Compiler optimizations; Loop tiling; Memory hierarchy optimization; Performance models; Quantitative case study

Indexed keywords

ARRAY PADDING; COMPILER OPTIMIZATION; LOOP TILING; MEMORY HIERARCHY OPTIMIZATION; PERFORMANCE MODELS; QUANTITATIVE CASE STUDY;

ALGORITHMS; BUFFER STORAGE; CODES (SYMBOLS); COMPUTER PROGRAM LISTINGS; COST BENEFIT ANALYSIS; DATA REDUCTION; DATA STORAGE EQUIPMENT; MATRIX ALGEBRA; PERFORMANCE; STABILITY;

PROGRAM COMPILERS;

EID: 1242352552     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:SUPE.0000011388.54204.8e     Document Type: Article

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