Study of electroplated compliant G-Helix chip-to-substrate interconnects

Advances in Electronic Packaging

Volumn 2, Issue , 2003, Pages 875-886

  Zhu, Qi ^a   Ma, Lunyu ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROPLATING; FLIP CHIP DEVICES; HEAT SINKS; MICROELECTRONICS; MICROPROCESSOR CHIPS; SOLDERING ALLOYS; THERMAL EXPANSION; ELECTRONIC EQUIPMENT MANUFACTURE; FABRICATION; OPTIMIZATION; PACKAGING; PHOTOLITHOGRAPHY; SILICON WAFERS;

RESPONSE SURFACE METHODOLOGY (RSM); UNDERFILL MATERIALS; COEFFICIENT OF THERMAL EXPANSION; CROSS-SECTION AREA; DIFFERENTIAL DISPLACEMENTS; ELECTRICAL PERFORMANCE; G-HELIX INTERCONNECTS; GEOMETRY EFFECTS; IC FABRICATION; LOWER COST; MECHANICAL COMPLIANCE; MICROSYSTEM PACKAGES; ORGANIC SUBSTRATE; ORTHOGONAL DIRECTIONS; PARASITICS; RESPONSE SURFACE METHODOLOGY; SILICON DIE; STAND OFF HEIGHT; TRADE OFF; UNDERFILLS; WAFER LEVEL; WAFER LEVEL PACKAGING; WAFER-LEVEL FABRICATION;

ELECTRONICS PACKAGING; CHIP SCALE PACKAGES;

EID: 1242286974     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/ipack2003-35342     Document Type: Conference Paper

References (18)

1. http://public.itrs.net, International Technology Roadmap for Semiconductors, 2001
2. Ghaffarian, R., "Chip-Scale Package Assembly Reliability", Chip Scale, November 1998
3. Chang, C.S., Oscilouski, A., and Bracken, R.C., "Future Challenges in Electronics packaging", Circuits & Devices, pp. 45-54, 1998
4. Zhu, Q., Ma, L., and Sitaraman, S. K., "Design and Fabrication of β-fly- a chip-to-substrate Interconnect", Proceeding of ASME International Mechanical Engineering Congress (ASME IMECE), November, 2002,
5. Gere J. M. and Timoshenko S. P., Mechanics of Material, 3rd ed., Boston: PWS, 1990, pp.675-685
6. Boresi, A. P., Sidebottom, O.M., Seely, F. B. and Smith. J. O, 1978, Advanced Mechanics of Materials, 4th ed. New York: Wiley, 1985, pp.184
7. Brown, W.D., Advanced Electronic Packaging, New York: IEEE Press, 1999, pp.95-96
8. Tummala, R. R., Fundamentals of Microsystems Packaging, New York: Mc-Graw-Hill, 2001,pp.124-125
9. Simpson, T.W., Peplinski, J., Koch, P. N. and Allen, J., " On the Use of Statistic in Design and the Implications for Deterministic Computer Experiments", ASME -DETC, pp.1-4, September 1997
10. Myers, R.H. and Montgomery, D.C., Response Surface Methodology: Process and Product Optimization Using Designed Experiments, 2d ed. New York: John Wiley & Sons, 1995, pp.336-337
11. Montgomery, D. C. and Runger, G. C., Applied Statistics and Probability for Engineers, 2d ed. New York: John Wiley & Sons, 1999, pp.312-313
12. Mechanical and Electrical Considerations of Compliant Interconnect, Intel Corporation, Internal Report, 2001
13. Design Expert Version .6.0.5 User's Manual, 2001
14. Assembly for the Compliant Interconnect, Intel Corporation, Internal Report, 2002
15. Hanna, C., Michaelides, S., Palaniappan, P., Baldwin, D., and Sitaraman, S. K., "Numerical and Experimental Study of the Evolution of Stresses in Flip-Chip Assemblies during Assembly and Thermal Cycling," Proc. of 49th Electronic Components and Technology conf, 1999, pp. 1001-1009
16. Microelectronics Packaging Materials Database, Center for Information and Numerical Data Analysis and Synthesis (CINDAS), Purdue University, 1999
17. Guo, Q., Cutiongco, E. C., Keer, L. M. and Fine, M. E., ' Thermomechanical Fatigue Life Prediction of 63Sn/37Pb Solder," Journal of Electronic Packaging, vol. 114, no. 2, pp145-150, 1992
18. Iannuzzelli, R., "Predicting Plated-Through-Hole Reliability in High-Temperature Manufacturing Process," Proc. of 41th Electronic Components and Technology conf., 1991, pp. 410-421