Clock net optimization using active shielding

European Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 265-268

  Kaul, Himanshu ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE SHIELDING; ACTIVE SHIELDS; CLOCK NET; IMPROVE PERFORMANCE; SHIELD WIRE; SIGNAL PROPAGATION DELAYS; SIGNAL WIRES;

CLOCKS; SHIELDING; WIRE;

OPTIMIZATION;

EID: 11944258202     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2003.1257123     Document Type: Conference Paper

References (6)

1. S. Morton, "On-chip Signaling", Special Topic Evening Session, Intl. Solid State Circuits Conference (ISSCC), 2002.
2. L. He and K. M. Lepak, "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization", Proc. Intl. Symposium on Physical Design, pp. 55-60, 2000.
3. Y. Massoud, et. al., "Layout techniques for minimizing onchip interconnect self inductance, " Proc. DAC, pp 566-571, 1998.
4. S. van Dijk and D. Hkly, "Reduction of Interconnect Delay by Exploiting Cross-talk", Proceedings of European Solid State Circuits Conference, 2001.
5. M. Kamon. M. Tsuk, and J. White, "FastHenry: A multipoleaccelerated 3-D inductance extraction program, " IEEE Trans. on MTT, pp. 1750-1758, Sep. 1999.
6. P. Restle, et. al., "A clock distribution network for microprocessors, " IEEE J. of Solid State Circuits, pp 792-799, May 2001. http://public. itrs. netI, T RS, 2001 update