A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites

Microelectronics Reliability

Volumn 45, Issue 2, 2005, Pages 349-354

  Man, Tsz Yin ^a   Chan, Mansun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

NONVOLATILE MEMORY (NVM) CELLS; NUMERICAL DEVICE SIMULATION; SHORT CHANNEL EFFECTS (SCE);

CAMERAS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRODES; LEAKAGE CURRENTS; PERSONAL DIGITAL ASSISTANTS; POLYSILICON;

DATA STORAGE EQUIPMENT;

EID: 11344264862     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.08.016     Document Type: Conference Paper

References (8)

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6. TM flash scaling limitation IEEE Int. Nonvolatile Memory Technol. Conf. Proc. 1998 6 7
7. M.H. White, Y. Yang, P. Ansha, and M.L. French A low voltage SONOS nonvolatile semiconductor memory technology IEEE Trans. on Components, Packaging, and Manufacturing Technol., Part A 20 2 1997 190 195
8. M.K. Cho, and D.M. Kim High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology IEEE Electron Dev. Lett. 21 8 2000 399 401