Code-based test generation for validation of functional processor descriptions

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2619, Issue , 2003, Pages 569-584

  Baray, Fabrice ^a,b   Codognet, Philippe ^b   Diaz, Daniel ^c   Michel, Henri ^a  

^a STMICROELECTRONICS   (France)

^b SORBONNE UNIVERSITÉ   (France)

^c UNIVERSITÉ PARIS 1 PANTHÉON SORBONNE   (France)

Author keywords

Code based test generation; Constraint solving techniques; Functional hardware verification

Indexed keywords

CODES (SYMBOLS); COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HARDWARE; LOGIC DESIGN; LOGIC PROGRAMMING; MICROPROCESSOR CHIPS; SOFTWARE TESTING; SYSTEM-ON-CHIP;

AUTOMATIC GENERATION; CONSTRAINT SOLVERS; CONSTRAINT SOLVING; DESIGN AND IMPLEMENTATIONS; HARDWARE VERIFICATION; MICROPROCESSOR DESIGNS; STMICROELECTRONICS; TEST GENERATIONS;

INTEGRATED CIRCUIT DESIGN;

EID: 11244250123     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-36577-x_41     Document Type: Article

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