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Volumn 3, Issue , 2004, Pages

Implementation of Walsh function generator of order 64 using LUT cascades

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC FUNCTIONS; READMACHER FUNCTIONS; WALSH FUNCTION;

EID: 11144347084     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (10)
  • 1
    • 0035717395 scopus 로고    scopus 로고
    • Novel FPGA implementations of Walsh-Hadamard transforms for signal processing
    • Dec.
    • A. Amira, A. Bouridane, P. Milligan, and M. Roula, "Novel FPGA implementations of Walsh-Hadamard transforms for signal processing", IEE Proc. Vision, Image, Signal Processing, vol. 148, no. 6, pp. 377-383, Dec. 2001.
    • (2001) IEE Proc. Vision, Image, Signal Processing , vol.148 , Issue.6 , pp. 377-383
    • Amira, A.1    Bouridane, A.2    Milligan, P.3    Roula, M.4
  • 9
    • 0013400341 scopus 로고    scopus 로고
    • A cascade realization of multiple-output function for reconfigurable hardware
    • Lake Tahoe, California, June
    • T. Sasao, M. Matsuura, and Y. Iguchi, "A cascade realization of multiple-output function for reconfigurable hardware", Int. Workshop on Logic Synthesis, Lake Tahoe, California, pp. 225-230, June 2001.
    • (2001) Int. Workshop on Logic Synthesis , pp. 225-230
    • Sasao, T.1    Matsuura, M.2    Iguchi, Y.3
  • 10
    • 4444239920 scopus 로고    scopus 로고
    • A method to decompose multiple-output logic functions
    • San Diego, California, June 2-6, (accepted for publication)
    • T. Sasao and M. Matsuura, ""A method to decompose multiple-output logic functions," 41st Design Automation Conference, San Diego, California, June 2-6, 2004, (accepted for publication)
    • (2004) 41st Design Automation Conference
    • Sasao, T.1    Matsuura, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.