Scalable pipeline insertion in floating-point units for FPGA synthesis

Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Volumn , Issue , 2003, Pages 421-426

  Ortiz, Irvin ^a   Jimenez, Manuel A ^a  

^a UNIVERSITY OF PUERTO RICO   (Puerto Rico)

Author keywords

Floating point arithmetic; FPGA; Scalable hardware; Variable pipeline

Indexed keywords

ALGORITHMS; AUTOMATION; COMPARATORS (OPTICAL); COMPUTER HARDWARE; DIGITAL ARITHMETIC; FREQUENCY MULTIPLYING CIRCUITS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

SCALABLE HARDWARE; VARIABLE PIPELINES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 1542347066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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