An architecture of small-scaled neuro-hardware using probabilistically coded pulse neurons

Electrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)

Volumn 139, Issue 4, 2002, Pages 48-55

  Kawashima, Takeshi ^a   Ishiguro, Akio ^b   Okuma, Shigeru ^b,c  

^a DENSO CORPORATION   (Japan)

^b NAGOYA UNIVERSITY   (Japan)

^c NAGOYA INDUSTRIAL SCIENCE RESEARCH INSTITUTE   (Japan)

Author keywords

Hardware miniaturization; Neuro hardware; Probabilistic coding digital circuit; Pulsed neuron

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL METHODS; FIELD PROGRAMMABLE GATE ARRAYS; NEURAL NETWORKS; PROBABILISTIC LOGICS;

HARDWARE MINIATURIZATION;

DIGITAL INTEGRATED CIRCUITS;

EID: 0036603635     PISSN: 04247760     EISSN: None     Source Type: Journal    
DOI: 10.1002/eej.1168     Document Type: Article

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