SET tolerant CMOS comparator

IEEE Transactions on Nuclear Science

Volumn 51, Issue 6 II, 2004, Pages 3609-3614

  Mikkola, E ^a   Vermeire, B ^b   Barnaby, H J ^a   Parks, H G ^a   Borhani, K ^b  

^a University of Arizona   (United States)

^b Ridgetop Group Inc   (United States)

Author keywords

Analog to digital converters (ADCs); Auto zeroing techniques; CMOS mixed signal circuits; Comparators; Folded cascode; Hardening by design; Hardness by design; Radiation hardening; Single event effects (SEEs); Single event transients (SETs)

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPARATOR CIRCUITS; COMPUTER SIMULATION; MATHEMATICAL MODELS; RADIATION HARDENING; TRANSIENTS;

AUTO-ZEROING TECHNIQUES; CMOS MIXED SIGNAL CIRCUITS; FOLDED CASCODE; HARDENING-BY-DESIGN; HARDNESS BY DESIGN; SINGLE-EVENT EFFECTS (SEE); SINGLE-EVENT TRANSIENTS (SET); SINGLE-EVENT UPSETS (SEU); SPICE SIMULATION;

CMOS INTEGRATED CIRCUITS;

EID: 11044235033     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839161     Document Type: Conference Paper

References (6)

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