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Volumn 51, Issue 12, 2004, Pages 2345-2355

Modeling and evaluation of positive-feedback source-coupled logic

Author keywords

High speed; Logic style; Model; MOS current mode logic (MCML); Power efficient; Source coupled logic

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK ANALYSIS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; OSCILLATORS (ELECTRONIC); TRANSISTORS;

EID: 10944256335     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838149     Document Type: Article
Times cited : (41)

References (37)
  • 1
    • 0031103510 scopus 로고    scopus 로고
    • "A 5-V single chip delta-sigma audio A/D converter with 111 dB dynamic range"
    • Mar
    • I. Fujimori et al., "A 5-V single chip delta-sigma audio A/D converter with 111 dB dynamic range," IEEE J. Solid-State Circuits vol. 32, pp. 329-336, Mar. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 329-336
    • Fujimori, I.1
  • 2
    • 0031356196 scopus 로고    scopus 로고
    • "Quadrature bandpass ΣΔ modulator for digital radio"
    • S. Jantzi, K. Martin, and A. Sedra, "Quadrature bandpass Σ Δ modulator for digital radio," IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1949, 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 1935-1949
    • Jantzi, S.1    Martin, K.2    Sedra, A.3
  • 3
    • 0026406221 scopus 로고
    • "A bit-stream digital-to-analog converter with 18-b resolution"
    • Dec
    • B. Kup, E. Dijkmans, P. Naus, and J. Sneep, "A bit-stream digital-to-analog converter with 18-b resolution," IEEE J. Solid-State Circuits, vol. 26, pp. 1757-1763, Dec. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 1757-1763
    • Kup, B.1    Dijkmans, E.2    Naus, P.3    Sneep, J.4
  • 6
    • 0027668154 scopus 로고
    • "Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs"
    • Sept
    • D. Allstot, S. Chee, S. Kiaei, and M. Shristawa, "Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs," IEEE Trans. Circuits Syst. I, vol. 40, pp. 553-563, Sept. 1993.
    • (1993) IEEE Trans. Circuits Syst. I , vol.40 , pp. 553-563
    • Allstot, D.1    Chee, S.2    Kiaei, S.3    Shristawa, M.4
  • 7
    • 0027576336 scopus 로고
    • "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits"
    • Apr
    • D. Su, M. Loinaz, S. Masui, and B. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 420-430, Apr. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 420-430
    • Su, D.1    Loinaz, M.2    Masui, S.3    Wooley, B.4
  • 8
    • 0002861250 scopus 로고
    • "Simulation of substrate coupling in mixed-signal MOS circuits"
    • S. Masui, "Simulation of substrate coupling in mixed-signal MOS circuits," in Proc. Symp. VLSI Circuits, 1992, pp. 42-43.
    • (1992) Proc. Symp. VLSI Circuits , pp. 42-43
    • Masui, S.1
  • 9
    • 0028384192 scopus 로고
    • "Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis"
    • Mar
    • B. Stanistic, N. Verghese, R. Rutenbar, L. Carley, and D. Allstot, "Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis," IEEE J. Solid-State Circuits, vol. 29, pp. 226-238, Mar. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 226-238
    • Stanistic, B.1    Verghese, N.2    Rutenbar, R.3    Carley, L.4    Allstot, D.5
  • 10
    • 0029182063 scopus 로고
    • "A feedback control circuit design technique to suppress power noise in high speed output driver"
    • Apr
    • C. Choy, C. Chan, and M. Ku, "A feedback control circuit design technique to suppress power noise in high speed output driver," in Proc. ISCAS, Apr. 1995, pp. 307-310.
    • (1995) Proc. ISCAS , pp. 307-310
    • Choy, C.1    Chan, C.2    Ku, M.3
  • 11
    • 0030689256 scopus 로고    scopus 로고
    • "Design procedure of low-noise high-speed adaptive output drivers"
    • C. Choy, C. Chan, M. Ku, and J. Povazanec, "Design procedure of low-noise high-speed adaptive output drivers," in Proc. ISCAS, 1997, pp. 1796-1799.
    • (1997) Proc. ISCAS , pp. 1796-1799
    • Choy, C.1    Chan, C.2    Ku, M.3    Povazanec, J.4
  • 14
    • 0026854590 scopus 로고
    • "Low-noise logic for mixed-mode VLSI circuits"
    • S. Kiaei and D. Allstot, "Low-noise logic for mixed-mode VLSI circuits," Microelectron. J., vol. 23, no. 2, pp. 103-114, 1992.
    • (1992) Microelectron. J. , vol.23 , Issue.2 , pp. 103-114
    • Kiaei, S.1    Allstot, D.2
  • 15
    • 0026901344 scopus 로고
    • "Synthesis techniques for CMOS folded source-coupled logic circuits"
    • Aug
    • S. Maskal, S. Kiaei, and D. Allstot, "Synthesis techniques for CMOS folded source-coupled logic circuits," IEEE J. Solid-State Circuits vol. 27, pp. 1157-1167, Aug. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 1157-1167
    • Maskal, S.1    Kiaei, S.2    Allstot, D.3
  • 16
    • 0030359216 scopus 로고    scopus 로고
    • "Digital circuit techniques for mixed analog/digital circuits applications"
    • Rodos, Greece
    • R. Sàez, M. Kayal, M. Declercq, and M. Schneider, "Digital circuit techniques for mixed analog/digital circuits applications," in Proc. ICECS, Rodos, Greece, 1996.
    • (1996) Proc. ICECS
    • Sàez, R.1    Kayal, M.2    Declercq, M.3    Schneider, M.4
  • 17
    • 0027816393 scopus 로고
    • "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise"
    • Dec
    • R. Senthinatan and J. Prince, "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise," IEEE J. Solid-State Circuits, vol. 28, pp. 1383-1388, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 1383-1388
    • Senthinatan, R.1    Prince, J.2
  • 18
    • 0030708976 scopus 로고    scopus 로고
    • "Current mode BiCMOS folded source-coupled logic circuits"
    • June
    • J. Kundan and S. Hasan, "Current mode BiCMOS folded source-coupled logic circuits," in Proc. ISCAS, June 1997, pp. 1880-1883.
    • (1997) Proc. ISCAS , pp. 1880-1883
    • Kundan, J.1    Hasan, S.2
  • 19
    • 0030708976 scopus 로고    scopus 로고
    • "Current-mode BiCMOS folded source-coupled logic circuits"
    • June
    • K. Jayabalan and S. R. Hasan, "Current-mode BiCMOS folded source-coupled logic circuits," in Proc. ISCAS, June 1997, pp. 1880-1883.
    • (1997) Proc. ISCAS , pp. 1880-1883
    • Jayabalan, K.1    Hasan, S.R.2
  • 20
    • 0030700944 scopus 로고    scopus 로고
    • "Design guidelines for CMOS current steering logic"
    • R. Saez, M. Kayal, M. Declercq, and M. Schneider, "Design guidelines for CMOS current steering logic," in Proc. ISCAS, 1997, pp. 1872-1875.
    • (1997) Proc. ISCAS , pp. 1872-1875
    • Saez, R.1    Kayal, M.2    Declercq, M.3    Schneider, M.4
  • 21
    • 0031234332 scopus 로고    scopus 로고
    • "CMOS current steering logic for low-voltage mixed-signal integrated circuits"
    • Sept
    • H. Ng and D. Allstot, "CMOS current steering logic for low-voltage mixed-signal integrated circuits," IEEE Trans. VLSI Syst., vol. 5, pp. 301-308, Sept. 1997.
    • (1997) IEEE Trans. VLSI Syst. , vol.5 , pp. 301-308
    • Ng, H.1    Allstot, D.2
  • 22
    • 0034251366 scopus 로고    scopus 로고
    • "Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits"
    • Aug
    • J. Kundan and S. Hasan, "Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits," IEEE Trans. Circuits Syst. II, vol. 47, pp. 810-817, Aug. 2000.
    • (2000) IEEE Trans. Circuits Syst. II , vol.47 , pp. 810-817
    • Kundan, J.1    Hasan, S.2
  • 25
    • 0037899025 scopus 로고    scopus 로고
    • "Design strategies for source coupled logic gares"
    • May
    • M. Alioto and G. Palumbo, "Design strategies for source coupled logic gares," IEEE Trans. Circuits Syst. I, vol. 50, pp. 640-654, May 2003.
    • (2003) IEEE Trans. Circuits Syst. I , vol.50 , pp. 640-654
    • Alioto, M.1    Palumbo, G.2
  • 26
    • 0025521549 scopus 로고
    • "Advances in bipolar VLSI"
    • Nov
    • G. R. Wilson, "Advances in bipolar VLSI," Proc. IEEE, vol. 78, pp. 1707-1719, Nov. 1990.
    • (1990) Proc. IEEE , vol.78 , pp. 1707-1719
    • Wilson, G.R.1
  • 27
    • 0024627385 scopus 로고
    • "DC analysis of current mode logic"
    • Mar
    • R. L. Treadway, "DC analysis of current mode logic," IEEE Circuits Devices Mag., vol. 5, pp. 21-35, Mar. 1989.
    • (1989) IEEE Circuits Devices Mag. , vol.5 , pp. 21-35
    • Treadway, R.L.1
  • 28
    • 0030166181 scopus 로고    scopus 로고
    • "Performance of CMOS differential circuits"
    • June
    • P. Ng, T. Balsara, and D. Steiss, "Performance of CMOS differential circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 841-846, June 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.31 , pp. 841-846
    • Ng, P.1    Balsara, T.2    Steiss, D.3
  • 29
    • 0026157328 scopus 로고
    • "High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic"
    • May
    • H. J. Greub, J. F. Mcdonald, T. Creedon, and T. Yamaguchi, "High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic," IEEE J. Solid-State Circuits, vol. 26, pp. 749-762, May 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 749-762
    • Greub, H.J.1    Mcdonald, J.F.2    Creedon, T.3    Yamaguchi, T.4
  • 30
    • 0028385097 scopus 로고
    • "Design techniques for low-voltage high speed digital bipolar circuits"
    • Mar
    • B. Razavi, Y. Ota, and R. Swartz, "Design techniques for low-voltage high speed digital bipolar circuits," IEEE J. Solid-State Circuits vol. 29, no. 2, pp. 332-339, Mar. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , Issue.2 , pp. 332-339
    • Razavi, B.1    Ota, Y.2    Swartz, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.