Architecture optimization for multimedia application exploiting data and thread-level parallelism

Journal of Systems Architecture

Volumn 51, Issue 1, 2005, Pages 15-27

  Limousin, Claude ^a   Sebot, Julien ^a   Vartanian, Alexis ^a   Drach, Nathalie ^a  

^a UFR 919 Laboratoire d'Informatique Pour la Mécanique et les Sciences de l'Ingénieur   (France)

Author keywords

Memory hierarchy; Multimedia; SIMD; SMT; Superscalar processor

Indexed keywords

DATA ACQUISITION; HIERARCHICAL SYSTEMS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PARALLEL ALGORITHMS; REAL TIME SYSTEMS;

MEMORY HIERARCHY; PARALLELISM; SUPERSCALAR PROCESSOR; TRIANGLES;

SYSTEMS ENGINEERING;

EID: 10844276274     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2004.06.002     Document Type: Article

References (27)

1. M. Abrash, InsideXbox Graphics. Available from 〈http:// www.ddj.com/articles/2000/0008/0008a/0008a.htm〉, 2000.
2. Apple, AltiVec Home Page. Available from 〈http://developper.apple. com/hardware/altivec〉, 1999.
3. J.-L. Bechennec, ASF: A teaching and research object-oriented simulation tool for computer architecture design and performance evaluation. Workshop on Computer Architecture Education of International Symposium on Computer Architecture, 1998.
4. R. Bhargava, L. John, B. Evans, R. Radhakrishnan, Evaluating mmx technology using dsp and multimedia applications, in: International Symposium on Microarchitecture, 1998, pp. 37-46.
5. R. Espasa, M. Valero, Simultaneous multithreaded vector architecture: Merging ilp and dip for high performance, in: International Conference on High Performance Computing, 1997, pp. 350-357.
6. S.R. Goldschmidt, J.L. Hennessy, The accuracy of trace-driven simulations of multiprocessors, in: Conference on Measuring and Modeling of Computer Systems, pp. 146-157.
7. M. Gulati, N. Bagherzadeh, Performance study of a multithreaded superscalar microprocessor, in: International Symposium on High-Performance Computer Architecture, 1996, pp. 291-301.
8. S. Hily, A. Seznec, Standard memory hierarchy does not fit simultaneous multithreading, Workshop on Multithreaded Execution Architecture and Compilation (in conjunction with International Symposium on High-Performance Computer Architecture), 1998.
9. H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, T. Nishizawa, An elementary processor architecture with simultaneous instruction issuing from multiple threads. International Symposium on Computer Architecture, 1992, pp. 136-145.
10. C. Limousin, A. Vartanian, J.-L. Bechennec, PopSpy: A PowerPC instrumentation tool for multiprocessor simulation, in: European Conference on Parallel Computing, 1999, pp. 262-256.
11. J.L. Lo, Exploiting thread-level parallelism on simultaneous multithreaded processors, Master's thesis, University of Washington, 1998.
12. M. Loikkanen, N. Bagherzadeh, A fine-grain multithreading superscalar architecture, International Conference on Parallel Architectures and Compilation Techniques, 1996, pp. 63-68.
13. P. Mark, M. Olano, J. Airey, P.J. Ungar, Interactive multi-pass programmable shading, Computer Graphics (2000).
14. Kurt Akeley Mark Segal, The OpenGL Graphics System: A Specification, Silicon Graphics inc., 1996.
15. Microsoft, Microsoft DirectX 3 SDK: Direct3D Overview, 1996.
16. Motorola, Motorola's high-performance vector parallel processing expansion to the PowerPC architecture. Available from 〈http://www.motorola. com/SPS/PowerPC/AltiVec/〉, 1999.
17. H. Nguyen, L.K. John, Exploting simd parallelism in dsp and multimedia algorithms using altivec technology. International Conference on Supercomputing, 1999, pp. 11-20.
18. H. Oehring, U. Sigmund, T. Ungerer, Mpeg-2 video decompression on simultaneous multithreaded multimedia processors, in: International Conference on Parallel Architectures and Compilation Techniques, 1999, pp. 11-16.
19. M. Oka, M. Suzuoki, Designing and programming the emotion engine, IEEE Micro 19 (6) (1999) 20-28.
20. M. Olano, A. Lastra, A shading language on graphics hardware: The pixelflow. Computer Graphics (1998) 159-168.
21. B. Paul, The mesa 3d-graphic library. Available from 〈interrefhttp:/ /www.mesa3d.orgurlhttp://www.mesa3d. org〉, 1999.
22. M. Pontius, N. Bagherzadeh, Multithreaded extensions enhance multimedia performance, Workshop on Multi-Threaded Execution, Architecture and Compilation, 1999.
23. P. Ranganathan, S. Adve, N. Jouppi, Performance of image and video processing with general-purpose processors and media isa extensions, in: International Symposium on Computer Architecture, 1999, pp. 124-135.
24. J. Sebot, A. Vartanian, J.-L. Bechennec, N. Drach-Temam, A parallel algorithm for 3D geometry transformations in opengl, in: European Conference on Parallel Computing, 1999, pp. 659-662.
25. D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, in: International Symposium on Computer Architecture, 1996, pp. 191-202.
26. D.M. Tullsen, S.J. Eggers, H.M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, in: International Symposium on Computer Architecture, 1995, pp. 392-403.
27. C.-L. Yang, B. Sano, A.R. Lebeck, Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications, in: International Symposium on Microarchitecture, 1998, pp. 37-46.