A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1866-1875

  Hoskote, Yatin ^a   Bloechel, Bradley A ^a   Dermer, Gregory E ^a   Erraguntla, Vasantha ^a   Finan, David ^a   Howard, Jason ^a   Klowden, Dan ^a   Narendra, Siva G ^a   Ruhl, Greg ^a   Tschanz, James W ^a   Vangal, Sriram ^a   Veeramachaneni, Venkat ^a   Wilson, Howard ^a   Xu, Jianping ^a   Borkar, Nitin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Gigabit ethernet; Offload; Packet processing; Special purpose processor; TCP

Indexed keywords

INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); LOCAL AREA NETWORKS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OPEN SYSTEMS; PACKET SWITCHING; RESPONSE TIME (COMPUTER SYSTEMS); TELECOMMUNICATION TRAFFIC;

ETHERNET; OFFLOAD ACCELERATOR; SPECIAL PURPOSE PROCESSOR;

CMOS INTEGRATED CIRCUITS;

EID: 10744230067     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818294     Document Type: Article

References (10)

1. A. Foong, T. Huff, H. Hum, J. Patwardhan, and G. Regnier, "TCP performance re-visited," in Proc. IEEE Int. Symp. Performance Analysis of Systems and Software, Mar. 2003, pp. 70-79.
2. J. Chase, A. Gallatin, and K. Yocum, "End system optimizations for high-speed TCP," IEEE Commun. Mag., vol. 39, pp. 68-74, Apr. 2001.
3. J. Kay and J. Pasquale, "Profiling and reducing processing overheads in TCP/IP networking," IEEE/ACM Trans. Networking, vol. 4, pp. 817-828, Dec. 1996.
4. M. Allman and A. Falk, "On the effective evaluation of TCP," ACM SIGCOMM Comput. Commun. Rev., vol. 29, no. 5, pp. 59-70, Oct. 1999.
5. Transmission Control Protocol NIC-RFC 793, DDN Protocol Handbook, vol. 2, Information Sciences Inst., Univ. Southern California, Los Angeles, Sept. 1981, pp. 2179-2198.
6. D. Clark, V. Jacobson, J. Romkey, and H. Salwen, "An analysis of TCP processing overhead," IEEE Commun. Mag., vol. 27, pp. 23-29, June 1989.
7. V. Paxson, "End-to-end internet packet dynamics," IEEE/ACM Trans. Networking, vol. 7, pp. 277-292, June 1999.
8. S. Mathew, M. Anders, R. Krishnamurthy, and S. Borkar, "A 4 GHz 130 nm address generation unit with a 32-bit sparse-tree adder core," in Proc. VLSI Circuits Symp., 2002, pp. 126-127.
9. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2001, pp. 147-151.
10. K. Kuhn, M. Agostinelli, S. Ahmed, S. Chambers, S. Cea, S. Christensen, P. Fischer, J. Gong, C. Kardas, T. Letson, L. Henning, A. Murthy, H. Muthali, B. Obradovic, P. Packan, S. Pae, I. Post, S. Putna, K. Raol, A. Roskowski, R. Soman, T. Thomas, P. Vandervoon, M. Weiss, and I. Young, "A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS," in IEDM Tech. Dig., 2002, pp. 73-76.