Modeling of single-event effects in circuit-hardened high-speed SiGe HBT logic

IEEE Transactions on Nuclear Science

Volumn 48, Issue 6 I, 2001, Pages 1849-1854

  Niu, Guofu ^a,b   Krithivasan, Ramkumar ^b   Cressler, John D ^a,b   Marshall, Cheryl ^a,c   Marshall, Paul ^a,c   Reed, Robert ^a,c   Harame, David L ^a,d  

^a IEEE   (United States)

^b AUBURN UNIVERSITY   (United States)

^c NASA GODDARD SPACE FLIGHT CENTER   (United States)

^d IBM MICROELECTRONICS   (United States)

Author keywords

Charge collection; Circuit modeling; Current mode logic; Heterojunction bipolar transistor (HBT); SiGe; Single event effects (SEEs)

Indexed keywords

CHARGE COLLECTION; SINGLE EVENT EFFECTS (SEE);

COMPUTER SIMULATION; DOPING (ADDITIVES); ELECTRIC CHARGE; EQUIVALENT CIRCUITS; FLIP FLOP CIRCUITS; IONS; RESISTORS; SEMICONDUCTING SILICON COMPOUNDS; SUBSTRATES;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0035721956     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.983141     Document Type: Conference Paper

References (8)

1. Single event effects in circuit hardened SiGe HBT logic at gigabit per second data rate
2. Simulation of SEE-induced charge collection in UHV/CVD SiGe HBT's
3. Device simulation of charge collection and single-event upset
4. Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace
5. Investigation of single-event upset (SEU) in an advanced bipolar process
6. Noise parameter optimization of UHV/CVD SiGe HBT's for RF and microwave applications