Realizing high-voltage junction isolated LDMOS transistors with variation in lateral doping

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2223-2228

  Hardikar, Shyam ^a   Tadikonda, Ramakrishna ^a   Green, David W ^a   Vershinin, Konstantin V ^a   Narayanan, Ekkanath Madathil Sankara ^a  

^a DE MONTFORT UNIVERSITY   (United Kingdom)

Author keywords

High voltage integrated circuits (HVIC); Junction isolation; Lateral diffused metal oxide semiconductor (LDMOS); Power ICs; Reduced surface field (RESURF); Variation in lateral doping (VLD)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; MATHEMATICAL MODELS; POWER INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

HIGH VOLTAGE INTEGRATED CIRCUITS; JUNCTION ISOLATION; LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR; REDUCED SURFACE FIELD; VARIATION IN LATERAL DOPING;

MOSFET DEVICES;

EID: 10644246046     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.839104     Document Type: Article

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