A CMOS Oversampling Bandpass Cascaded D/A Converter With Digital FIR and Current-Mode Semi-Digital Filtering

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 4, 2004, Pages 585-593

  Barkin, David B ^a   Lin, Andrew C Y ^a   Su, David K ^a   Wooley, Bruce A ^a  

^a Stanford University   (United States)

Author keywords

Bandpass digital to analog conversion; CMOS integrated circuits; Data weighted averaging; Digital analog conversion; Mixed analog digital integrated circuits; Noise shaping; Oversampling; Semi digital filtering; Sigma delta modulation; Transmitters

Indexed keywords

DELTA SIGMA MODULATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; LOW PASS FILTERS; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; TRANSMITTERS; WIRELESS TELECOMMUNICATION SYSTEMS;

BANDPASS DIGITAL-TO-ANALOG CONVERSION; DATA-WEIGHTED AVERAGING; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS; NOISE SHAPING; OVERSAMPLING; SEMI-DIGITAL FILTERING;

CMOS INTEGRATED CIRCUITS;

EID: 10444275356     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.825245     Document Type: Article

References (14)

1. L. R. Carley, "A noise-shaping coder topology for 15+ bit converters," IEEE J. Solid-State Circuits, vol. 24, pp. 267-273, Apr. 1989.
2. C. C. Cutler, "Transmission systems employing quantization," U.S. Patent 2,927,962, Mar. 8, 1960.
3. L. Williams and B. Wooley, "Third-order cascaded sigma-delta modulators." IEEE Trans. Circuits Syst., vol. 38, pp. 489-498, May 1991.
4. X. Xu, G. Temes, and R. Schreier, "The implementation of dual-truncation ∑ δ D/A converters," in Proc. IEEE Int. Symp. Circuits and Systems Conf., May 1992, pp. 597-600.
5. D. Su and B. Wooley, "A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter," IEEE J. Solid-State Circuits, vol. 28, pp. 1224-1233, Dec. 1993.
6. T. Shui, R. Schreier, and F. Hudson, "Mismatch shaping for a current-mode multibit delta-sigma DAC," IEEE J. Solid-State Circuits, pp. 331-338, Mar. 1999.
7. H. Tuinhout and M. Vertregt, "Test structures for investigation of metal coverage effects on Mosfet matching," in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 10, Mar. 1997, pp. 179-183.
8. A. Hastings, The Art of Analog Layout. Upper Saddle River, NJ: Prentice-Hall, 2001, pp. 430-442.
9. Y. Cong and R. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays." IEEE Trans. Circuits Syst. II, vol. 47, pp. 585-595, July 2000.
10. K. Falakshahi, C. Yang, and B. Wooley, "A 14-bit, 10-Msamples/s D/A converter using multibit ∑ δ modulation," IEEE J. Solid-State Circuits, vol. 34, pp. 607-615, May 1999.
11. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
12. T. Miki et al., "An 80-MHz 8-bit CMOS D/A converter," IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, Dec. 1986.
13. R. Adams, K. Nguyen, and K. Sweetland, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling," IEEE J. Solid-State Circuits, vol. 33, pp. 1871-1878, Dec. 1998.
14. S. Norsworthy, R. Schreier, and G. Ternes, Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, 1997, pp. 401-402.